With out DMA, when the CPU is utilizing programmed enter/output, it is often fully occupied for the entire duration of the learn or write operation, and is thus unavailable to perform other work. With DMA, the CPU first initiates the switch, then it does different operations whereas the transfer is in progress, and it lastly receives an interrupt from the DMA controller (DMAC) when the operation is completed. This function is useful at any time that the CPU can not sustain with the rate of information transfer, or when the CPU must perform work whereas ready for a relatively slow I/O knowledge transfer. Many hardware methods use DMA, including disk drive controllers, graphics cards, network playing cards and sound playing cards. DMA is also used for intra-chip data switch in some multi-core processors. Computer systems which have DMA channels can transfer knowledge to and from gadgets with much much less CPU overhead than computer systems without DMA channels. Equally, a processing circuitry inside a multi-core processor can switch data to and from its local memory without occupying its processor time, allowing computation and data switch to proceed in parallel.
DMA will also be used for "memory to memory" copying or moving of information within Memory Wave Workshop. DMA can offload costly memory operations, comparable to large copies or scatter-gather operations, from the CPU to a dedicated DMA engine. An implementation instance is the I/O Acceleration Technology. DMA is of curiosity in network-on-chip and in-memory computing architectures. Commonplace DMA, additionally referred to as third-occasion DMA, uses a DMA controller. A DMA controller can generate memory addresses and provoke memory learn or write cycles. It accommodates a number of hardware registers that may be written and browse by the CPU. These embrace a memory tackle register, a byte depend register, and one or more management registers. Relying on what options the DMA controller offers, these management registers might specify some combination of the supply, the vacation spot, the course of the switch (studying from the I/O system or writing to the I/O gadget), the size of the transfer unit, and/or the variety of bytes to transfer in one burst.
To perform an enter, output or memory-to-memory operation, the host processor initializes the DMA controller with a count of the variety of phrases to switch, and the memory tackle to use. The CPU then commands the peripheral device to provoke an information transfer. The DMA controller then supplies addresses and browse/write management strains to the system memory. Each time a byte of information is ready to be transferred between the peripheral system and memory, the DMA controller increments its internal tackle register until the complete block of knowledge is transferred. Some examples of buses using third-celebration DMA are PATA, USB (before USB4), and SATA